
package Muxes

import chisel3._
import chisel3.util._


class Muxes extends Module{
  val io = IO (new Bundle{
    val in_sels = Input(Vec(2, Bool()))
    val in_bits = Input(Vec(2, UInt(8.W)))
    val out1 = Output(UInt(8.W))
    val out2 = Output(UInt(8.W))
  })

  io.out1 := PriorityMux(io.in_sels, io.in_bits)  //lowest-index asserted select signal.
  io.out2 := Mux1H(io.in_sels, io.in_bits)
}

object Muxes_Gen extends App {
  println("Generating the adder hardware")
  (new chisel3.stage.ChiselStage).emitVerilog(new Muxes(),Array("--target-dir", "generated/ChiselStudy/Muxes"))
}